An embodiment relates to semiconductor processing. One embodiment in particular relates to a process for making a silicon-on-insulator ledge structure that includes a partially isolated active area in a semiconductive substrate.
Semiconductor processing is an intensive activity during which several processes are integrated to achieve a working device. Miniaturization is the process of crowding more semiconductive devices onto a smaller substrate area in order to achieve better device speed, lower energy usage, and better device portability, among others. New processing methods must often be developed to enable miniaturization to be realized. Preferably, the processing methods needed to fabricate such devices are developed in a manner that existing processing equipment can be used.
The pressure to continue the miniaturization process also leads to new semiconductor device structures. As individual active devices become smaller and are fabricated closer together, leakage and second order effects become more significant. In the field of metal oxide semiconductor field-effect transistors (MOSFET), device leakage and miniaturization appear to be antagonistic challenges. Often, oxidation is carried out for the purpose of isolation, but oxidation often imparts stresses in the workpieces that lead to device failure. Deposition processes, although necessary, are time-consuming and costly. Further, deposition processes require masking and careful application. Further, deposition processes are preferentially applied when an integrated process can take advantage of a given deposition simultaneously in unrelated areas of a device.
The above mentioned problems and challenges are overcome by embodiments of this invention. One embodiment is directed to a process of forming a partially isolated structure of sufficient size to permit the fabrication of an active device thereon. The process includes forming an etch-selective region in the semiconductive workpiece that restricts the effects of an isotropic etch. The etch-selective region is created by implantation that causes the semiconductive material to become amorphous.
Protective material, such as a polysilicon layer and a nitride layer, is deposited over a pad oxide layer to protect the pad oxide layer. An active area is defined by patterning a mask. The protective material, the pad oxide layer, and finally the substrate are etched to form a trench around the active area. A protective film that is typically nitride material, is formed upon exposed silicon. The substrate is etched to deepen the trench around what will become the active area to a level below the protective layer. The etch-selective implantation region is either then formed or exposed by the previous etch. An isotropic etch follows that acts to substantially insulate the active area by its undercutting effect. The implantation region is annealed to repair the crystal lattice of the substrate. Thereafter, an alternative oxidation process is done to further isolate the active area from adjacent active areas or other structures. Oxide spacers are formed on the sides of the active area, and the remainder of the trench is filled to form a shallow trench isolation (STI) structure.
An embodiment is also directed to a partially isolated structure of sufficient size to permit the fabrication of an active device thereon. The partially isolated structure is comprised of a portion of the a substrate that has an undercut lateral cavity that is shaped in a manner which defines the active area of the partially isolated structure.
The process and structure of various embodiments enable active devices to be packed into ultra-dense configurations using currently available fabrication equipment. Because the diode junctions of active devices are formed in areas of the substrate that are at least partially isolated from the remainder of the substrate, the diode junctions may be fabricated to be less leaky.